Electronic apparatuses, such as semiconductor Integrated Circuits (ICs), can be classified in different categories, depending on the voltage differences that occur across the terminals of semiconductor devices included therein. In general, these voltage differences may be higher than a supply voltage of the IC or not.
More specifically, “standard” digital ICs—for example, logic circuits belonging to the Complementary Metal Oxide Semiconductor (CMOS) class—have to handle voltages that are usually equal to or lower than the supply voltage. Said ICs can be implemented with low voltage transistors designed in such a way to be able to sustain (across their terminals) maximum voltage differences that (in absolute value) equal to the supply voltage. Indeed, the low voltages that are experienced by those transistors allow their correct functioning (without breaking down) in any condition. For example, low voltage Metal Oxide Semiconductor (MOS) transistors are designed in such a way to avoid the occurrence of gate oxide break down or undesired junction breakdown when low voltage differences are applied to their terminals (for example, between the gate and source terminals).
Conversely, there exists a great variety of ICs that manage voltages that are higher than the supply voltage in absolute value—for example, non-volatile memories. In particular, in the non-volatile memories' high voltages are used to modify the data stored in their cells—e.g., to program and/or erase the cells, by activating known physical phenomena such as Channel Hot Electron (CHE) injection and Fowler-Nordheim Tunneling (FNT). The transistors used in such ICs are capable of withstanding high voltage differences across their terminals, without damage or malfunctioning, for example, to prevent gate oxides from breaking down or junction breakdown, or to prevent triggering undesired CHE injection or FNT.
As a consequence, referring for example to the case of MOS ICs, high voltage MOS transistors are designed, engineered and integrated (with ad-hoc manufacturing process steps) in such a way to avoid the occurrence of gate oxide break down or undesired junction breakdown even when high voltage differences are applied to their terminals (and especially between the gate and source terminals). In particular, high voltage MOS transistors have a gate oxide layer thicker than that normally used for the standard low voltage MOS transistors. Indeed, the thicker the gate oxide layer, the higher the voltage that it can sustain without undesired break down.
However, the use of high voltage transistors may pose constraints to the technology used to fabricate the IC. More particularly, even if the scaling of the transistors size, made possible by the evolution of the manufacturing technologies, allows drastically reducing the sizes of the low voltage transistors, the gate oxide layer of the high voltage transistors typically cannot be thinned, without putting at risk their capability of sustaining the desired voltages. Consequently, it may not be possible to shrink the sizes of the high voltage transistors, and thus it may be difficult to achieve the desired reduction in the silicon area occupied by those ICs including high voltage transistors.
Moreover, the use of both low voltage and high voltage transistors may increase the number of processing steps and masks (for example, for differentiating the oxide thickness of the high and low voltage transistors); this may have a detrimental impact on the manufacturing process of the memory device.